A single flux quantum (SFQ) circuit in which a single flux quantum (Φ0=h/2e=2.05×10−15 Weber) is used as an information carrier is a superconducting circuit that is characterized by: ultrahigh-speed operation whose speed is in the order of several tens of gigahertz (109 Hz) or higher; and low-power property whose level is in the order of several microwatts (μW) per gate or lower. On the basis of the principles shown in IEEE Transaction Applied Superconductivity, Vol. 1, No. 1 (1991) p. 3, various kinds of logic gates have been developed so far, and circuits for practical use for which these logic gates are used in combination are widely being developed.
Applications of the SFQ circuit include an analog-to-digital converter. In order to make full use of high speed that is an advantage of the SFQ circuit, an oversampling method is adopted as a conversion method. Specifically, an analog signal is sampled with the frequency that is sufficiently higher than a band width, and the low bit accuracy (oversampling). Next, a sampling data signal is subjected to signal processing by use of a decimation filter, so that a digital signal with high accuracy is acquired in a required frequency band width.
As regards the oversampling method based on the SFQ circuit, the sigma-delta modulation is disclosed in the specification of U.S. Pat. No. 5,140,324 and in IEEE Transaction Applied Superconductivity, Vol. 3, No. 1, (1993), pp. 2732. In addition, the delta modulation is disclosed in IEEE Transaction Applied Superconductivity, Vol. 5, No. 2, (1995), pp. 2252.
In general, a SFQ circuit propagates a SFQ clock signal in the form of a SFQ pulse train to each SFQ function circuit so that the operation timing of the SFQ function circuit forming the SFQ circuit is aligned. Here, the SFQ function circuit is one of circuit elements constituting the SFQ circuit. The SFQ function circuit is a circuit having a unified series of workings, such as a comparator circuit, a reset-set flip-flop circuit, and an analog-to-digital converter, which will be described later. Each SFQ function circuit makes use of the supplied SFQ clock signal as a trigger signal so as to synchronize circuit operation with the SFQ clock signal. The same SFQ clock signal is supplied to a plurality of SFQ function circuits from one clock signal source and thereby it is possible to synchronize the operation of each SFQ function circuit with one SFQ clock signal.
Also in the case where the SFQ circuit is applied to the A/D converter, a SFQ clock signal having a frequency of several tens of gigahertz or higher is supplied, as an oversampling clock signal, to an analog-signal sampling circuit and a modulator, each of which includes a SFQ circuit.
To generate a SFQ clock signal, two kinds of methods have been proposed so far: a method that uses a semiconductor oscillator located outside a SFQ circuit; a method that uses a ring oscillator located inside a SFQ circuit.
FIG. 1A is a diagram illustrating a clock-signal supply circuit based on the former method; and FIG. 1B is a diagram illustrating as an example a dc-to-SFQ converter circuit used in the clock-signal supply circuit. In addition, FIG. 1C is a diagram illustrating each waveform in the circuit.
First of all, a semiconductor oscillator 101 generates a current clock signal 110 that is a sine wave or a rectangular wave. FIG. 1C shows a trapezoidal wave as an example. The generated current clock signal is transmitted through a coaxial cable, a microstrip line, or the like, to a SFQ circuit 102 kept in a cold-temperature environment. In the SFQ circuit 102, the current clock signal is converted into a SFQ clock signal 111 by a dc/SFQ converter 103.
In the dc/SFQ converter 103 shown in FIG. 1B, the current clock signal 110 is induced into a quantizing inductor 125 coupled magnetically to an input inductor 122. This causes a circular current 126 to flow clockwise through a superconducting loop that is formed of the quantizing inductor 125, a Josephson junction 123 and a Josephson junction 124. With the increase in current level of the inputted current clock signal 110, the circular current 126 induced on the superconducting loop side also increases in like manner. When the total amount of this circular current 126 and an electric current from the bias current source 121 becomes greater than a critical current value of the Josephson junction 123, the Josephson junction 123 changes to a voltage-state. As a result, an electric current flows from the Josephson junction 123 to the Josephson junction 124, and also flows to the output end of the converter. The electric current flowing toward the Josephson junction 124 becomes a counterclockwise circular current 127 permanently flowing through the superconducting loop that is formed of the Josephson junction 123, the Josephson junction 124 and the inductor 125. Because this circular current 127 flows in a direction opposite to the direction of the circular current 126 induced by the input current clock signal, the circular current 126 is lost in appearance, and accordingly an electric current flowing through the Josephson junction 123 becomes smaller than the critical current value. Therefore, the Josephson junction in a voltage-state returns to a zero-voltage-state again. The operation in which the Josephson junction changes from the zero-voltage-state to the voltage-state before returning to the zero-voltage-state again is hereinafter expressed as “a junction is switched”. This switching of the junction is performed in several picoseconds, causing a SFQ pulse, which is a voltage pulse, to be generated at a node 128 connecting with the bias current source 121.
On the other hand, when a level of the input current clock signal turns from increasing to decreasing, the circular current 126 flowing clockwise decreases and the circular current 127 flowing counterclockwise begins to increase. If this circular current 127 exceeds the critical current value of the Josephson junction 124, the Josephson junction 124 is switched and consequently the circular current 127 is lost. At this point of time, the circuit returns to an initial state.
To be more specific, at the moment when a current level at the rising edge of the inputted current clock signal exceeds the threshold value of the converter, one SFQ pulse is generated. Accordingly, if the current clock signal 110 is inputted into the dc/SFQ converter 103, a SFQ pulse train whose interval is the same as a period of the inputted current clock signal is obtained. This SFQ pulse train is used as the SFQ clock signal 111.
The generated SFQ clock signal 1111 is transmitted to a splitter circuit 105 through a Josephson transmission line 1041, and is then copied to two SFQ clock signals 1112, 1113, which are transmitted to SFQ function circuits 1061 and 1062 through Josephson transmission lines 1042 and 1043, respectively. FIG. 1A is based on the assumption that the SFQ clock signal is divided into the two SFQ function circuits 1061 and 1062.
On the other hand, FIG. 2A is a diagram illustrating a clock-signal supply circuit based on the latter generation method for generating a SFQ clock signal; and FIG. 2B is a diagram illustrating each waveform in the circuit.
As shown in FIG. 2A, a dc/SFQ converter 201 converts a current trigger signal 220 supplied from the outside into a SFQ trigger signal 2211 formed of one SFQ pulse. The SFQ trigger signal 2211 is propagated through a Josephson transmission line 202, and is then supplied to a ring oscillator circuit 200 as a SFQ trigger signal 2212. The ring oscillator circuit 200 starts oscillation operation by the SFQ trigger signal 2212. The SFQ trigger signal 2212 inputted from a confluence buffer 204 passes through a Josephson transmission line 2031 as a SFQ trigger signal 2213. When a SFQ trigger signal 2214 output from the Josephson transmission line 2031 passes through the splitter circuit 205, one SFQ clock signal 2221 is newly copied, and the copied signal is then output from the ring oscillator circuit 200. The original SFQ trigger signal 2214 is output from the splitter circuit 205 as a SFQ trigger signal 2215, and passes through a Josephson transmission line 2032, and is then output as a SFQ trigger signal 2216. The SFQ trigger signal 2216 returns to the confluence buffer 204, and is output as the SFQ trigger signal 2213 again. Accordingly, the SFQ trigger signal 2212 inputted into the ring oscillator circuit 200 passes around the Josephson transmission lines 2031, 2032, each of which is located in a ring shape. As a result, a SFQ pulse train is obtained from the splitter circuit 205. The SFQ pulse train obtained by the ring oscillator circuit 200 is used as the SFQ clock signal 2221; and a SFQ clock signal 2222 is transmitted to a splitter circuit 207 through a Josephson transmission line 2061. In the splitter circuit 207, two SFQ clock signals 2223, 2224 are obtained. These SFQ clock signals 2223 and 2224 are supplied to SFQ function circuits 2081 and 2082 as SFQ clock signals 2225 and 2226 through Josephson transmission lines 2062 and 2063, respectively. An interval of the SFQ pulse train coincides with a period during which a SFQ passes through the Josephson transmission line 203. Accordingly, the length of the Josephson transmission line 203 is adjusted so as to generate a SFQ clock signal whose frequency is in the order of several tens of gigahertz.